Paper Info
Title
Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification.
Abstract
This paper presents an in-situ storage topology for ultra-high-speed burst mode imagers, enabling low noise operation while keeping a high frame depth. The proposed pixel architecture contains a 4T pinned photodiode, a correlated double sampling (CDS) amplification stage, and an in-situ memory bank. Focusing on the sampling noise, the system level trade-off of the proposed pixel architecture is discussed, showing its advantages on the noise, power, and scaling capability. Integrated with an AC coupling CDS stage, the amplification is obtained by exploiting the strong capacitance to the voltage relation of a single NMOS transistor. A comprehensive noise model is developed for optimizing the trade-off between the area and noise. As a proof-of-concept, a prototype imager with a 30 mu m pixel pitch was fabricated in a CMOS 130 nm technology. A 108-cell memory bank is implemented allowing dense layout and parallel readout. Two types of CDS amplification stages were investigated. Despite the limited memory capacitance of 10 fF/cell, the photon transfer curves of both pixel types were measured over different operation speeds up to 20 Mfps showing a noise performance of 8.4 e(-)
Year
DOI
Venue
2018
10.3390/s18113683
SENSORS
Keywords
Field
DocType
image sensors,in-situ storage,ultra-high-speed imaging,burst mode,million frames per second,in-pixel amplification
In situ,Burst mode (photography),Electronic engineering,CMOS,Pixel,Engineering
Journal
Volume
Issue
ISSN
18
11
1424-8220
Citations 
PageRank 
References 
0
0.34
9
Authors
8
Name
Order
Citations
PageRank
Linkun Wu100.34
David San Segundo Bello200.34
Philippe Coppejans300.34
Jan Craninckx4756181.43
Andreas Suss511.30
Maarten Rosmeulen621.62
Piet Wambacq752996.10
Jonathan Borremans822130.47