Name
Abstract | ||
|---|---|---|
This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equation for transistor width tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1587/transfun.E101.A.2222 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | Field | DocType |
D-Flip-Flop, variation aware design, regression analysis | Regression analysis,Arithmetic,Theoretical computer science,Design methods,Flip-flop,Mathematics | Journal |
Volume | Issue | ISSN |
E101A | 12 | 1745-1337 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shinichi Nishizawa | 1 | 1 | 2.13 |
| Hidetoshi Onodera | 2 | 455 | 105.29 |