Name
Abstract | ||
|---|---|---|
Growing reverse-engineering attempts to steal or violate a design intellectual property (IP), or to identify the device technology in order to counterfeit integrated circuits (ICs), raise serious concerns in the IC design community. As the information derived from these practices can be used in a number of malicious ways, various active techniques have been proposed and deployed to protect IP, of ... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TCAD.2018.2801240 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
Integrated circuits,Logic gates,Design for testability,Discrete Fourier transforms,Reverse engineering,Automatic test pattern generation,Hardware | Design for testing,Testability,Automatic test pattern generation,Logic gate,Hardware security module,Computer science,Integrated circuit design,Computer hardware,Hardware obfuscation,Integrated circuit | Journal |
Volume | Issue | ISSN |
37 | 12 | 0278-0070 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michael Chen | 1 | 0 | 0.34 |
| Elham Moghaddam | 2 | 79 | 7.05 |
| Nilanjan Mukherjee | 3 | 801 | 57.26 |
| Janusz Rajski | 4 | 2460 | 201.28 |
| Jerzy Tyszer | 5 | 838 | 74.98 |
| Justyna Zawada | 6 | 20 | 3.48 |