Paper Info
Title
A Transient Noise Analysis of Secured Dual-Rail Based Logic Style
Abstract
Dual-rail logic circuits have been used as an effective countermeasure towards a more secure circuit design. However, with technology scaling and lowering of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , they lose interest as the signal reduction is less significant compared to CMOS. In this work, we revisit dual-rail logic designs (more specifically DDSLL) while focusing on intrinsic physical device noise using a transient noise analysis methodology and show that there exists a potential for such circuits to reduce the signal and concretely increase the noise. Our analysis, which extends to meaningful cryptographic figures-of-merit (FoMs) such as the SNR (Signal-to-Noise ratio) and Mutual-Information (MI), better clarifies the potential of DDSLL circuits to leverage the noise.
Year
DOI
Venue
2018
10.1109/NGCAS.2018.8572199
2018 New Generation of CAS (NGCAS)
Keywords
Field
DocType
dual-rail logic designs,intrinsic physical device noise,transient noise analysis methodology,DDSLL circuits,secured dual-rail based logic style,dual-rail logic circuits,technology scaling,signal reduction,signal-to-noise ratio,circuit design,cryptographic figures-of-merit,dynamic differential switching level logic
Logic gate,Technology scaling,Existential quantification,Cryptography,Computer science,Circuit design,Electronic engineering,CMOS,Transient noise,Electronic circuit
Conference
ISBN
Citations 
PageRank 
978-1-5386-7682-0
0
0.34
References 
Authors
0
4
Name
Order
Citations
PageRank
Kashif Nawaz100.68
Itamar Levi26710.38
François-Xavier Standaert33070193.51
Denis Flandre431670.47