Name
Abstract | ||
|---|---|---|
High-Level Synthesis (HLS) tools enable rapid hardware development, but design expertise and effort are necessary to tune the high-level descriptions into optimized circuits. To improve designer productivity, automated design-space exploration techniques have been proposed. However, the optimization processes sample expensive CAD flows. In this paper, we adapt multi-fidelity optimization methods to incorporate low-fidelity estimates available in the FPGA CAD flow and speed up tuning of HLS parameters. We find that multi-fidelity optimization techniques can significantly reduce optimization time compared to previous approaches. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/FPL.2018.00054 | 2018 28th International Conference on Field Programmable Logic and Applications (FPL) |
Keywords | Field | DocType |
multi-fidelity,optimization,variable fidelity,High-Level Synthesis,FPGA,Field Programmable Gate Arrays,HLS | CAD,Computer architecture,Fidelity,Computer science,Parallel computing,High-level synthesis,Field-programmable gate array,Solid modeling,Electronic circuit,Cad flow,Speedup | Conference |
ISSN | ISBN | Citations |
1946-147X | 978-1-5386-8518-1 | 0 |
PageRank | References | Authors |
0.34 | 2 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Charles Lo | 1 | 7 | 2.17 |
| Paul Chow | 2 | 868 | 119.97 |