Name
Abstract | ||
|---|---|---|
Due to many state-holding elements in asynchronous circuits, many faults need two-pattern tests. This paper presents a test methodology (DR-scan) for dual-rail asynchronous circuits. Our design for testability is a full-scan, clock-less technique that supports both one-pattern and two-pattern tests for single stuck-at faults. DR-scan is able to test memory elements in dual-rail logic without break... |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/TCAD.2018.2801226 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
Latches,Asynchronous circuits,Logic gates,Inverters,Registers,Encoding,Circuit faults | Design for testing,Code coverage,Automatic test pattern generation,Test method,Asynchronous communication,Logic gate,Computer science,Electronic engineering,Electronic circuit,Computer engineering,Encoding (memory) | Journal |
Volume | Issue | ISSN |
38 | 1 | 0278-0070 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shih-An Hsieh | 1 | 0 | 0.68 |
| Ying-Hsu Wang | 2 | 0 | 0.34 |
| Ting-Yu Shen | 3 | 0 | 1.01 |
| Kuan-Yen Huang | 4 | 0 | 0.68 |
| Chia-Cheng Pai | 5 | 0 | 0.34 |
| Tsai-Chieh Chen | 6 | 0 | 0.34 |
| James Chien-Mo Li | 7 | 187 | 27.16 |