Name
Abstract | ||
|---|---|---|
The poor quality of the die stacking process for 3-D integrated circuits can result in the failure of the process in the through-silicon-vias (TSVs) in dense regions. Previous works use the same number of redundant TSVs and architectures that do not consider the TSV density. A repair architecture and an appropriate number of redundant TSVs, which are chosen considering the TSV density, are require... |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/TCAD.2018.2808453 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
Through-silicon vias,Maintenance engineering,Circuit faults,Computer architecture,Delays,Merging,Standards | Architecture,Computer architecture,Computer science,Electronic engineering,Repair rate,Merge (version control),Integrated circuit,Maintenance engineering,Stacking | Journal |
Volume | Issue | ISSN |
38 | 1 | 0278-0070 |
Citations | PageRank | References |
1 | 0.37 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jaewon Jang | 1 | 1 | 1.38 |
| Minho Cheong | 2 | 2 | 1.08 |
| Sungho Kang | 3 | 436 | 78.44 |