Name
Abstract | ||
|---|---|---|
This paper describes flexible tools and techniques that can be used to efficiently design/generate quite a variety of hardware IP blocks for highly parameterized real-time video processing algorithms. The tools and techniques discussed in the paper include host software, FPGA interface IP (PCIe, USB 3.0, DRAM), high-level synthesis, RTL generation tools, synthesis automation as well as architectural concepts (e.g., nested pipelining), an architectural estimation tool, and verification methodology. The paper also discusses a specific use case to deploy the mentioned tools and techniques for hardware design of an optical flow algorithm. The paper shows that in a fairly short amount of time, we were able to implement 11 versions of the optical flow algorithm running on 3 different FPGAs (from 2 different vendors), while we generated and synthesized several thousand designs for architectural trade-off. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1007/s11265-018-1402-7 | Signal Processing Systems |
Keywords | Field | DocType |
Hardware IP generation,Real-time video processing,High-level synthesis,FPGA,Optical flow,Nested pipelining | Pipeline (computing),Video processing,Computer science,High-level synthesis,Field-programmable gate array,Algorithm,Automation,Software,PCI Express,USB | Journal |
Volume | Issue | ISSN |
91 | 1 | 1939-8115 |
Citations | PageRank | References |
0 | 0.34 | 12 |
Authors | ||
9 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vecdi Emre Levent | 1 | 0 | 0.34 |
| Aydin E. Guzel | 2 | 0 | 0.34 |
| Mustafa Tosun | 3 | 0 | 0.34 |
| Mert Buyukmihci | 4 | 0 | 0.34 |
| Furkan Aydin | 5 | 0 | 0.34 |
| Sezer Gören | 6 | 64 | 11.62 |
| Cengiz Erbas | 7 | 32 | 8.33 |
| Toygar Akgun | 8 | 90 | 9.39 |
| H. Fatih Ugurdag | 9 | 52 | 11.28 |