Name
Abstract | ||
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In recent years, Convolutional Neural Networks (CNNs) have been widely applied in computer vision and have achieved significant improvements in object detection tasks. Although there are many optimizing methods to speed up CNN-based detection algorithms, it is still difficult to deploy detection algorithms on real-time low-power systems. Field-Programmable Gate Array (FPGA) has been widely explored as a platform for accelerating CNN due to its promising performance, high energy efficiency, and flexibility. Previous works show that the energy consumption of CNN accelerators is dominated by the memory access. By fusing multiple layers in CNN, the intermediate data transfer can be reduced. However, previous accelerators with the cross-layer scheduling are designed for a particular CNN model. In addition to the memory access optimization, the Winograd algorithm can greatly improve the computational performance of convolution.
In this article, to improve the flexibility of hardware, we design an instruction-driven CNN accelerator, supporting the Winograd algorithm and the cross-layer scheduling, for object detection. We modify the loop unrolling order of CNN, so that we can schedule a CNN across different layers with instructions and eliminate the intermediate data transfer. We propose a hardware architecture to support the instructions with Winograd computation units and reach the state-of-the-art energy efficiency. To deploy image detection algorithms onto the proposed accelerator with fixed-point computation units, we adopt the fixed-point fine-tune method, which can guarantee the accuracy of the detection algorithms.
We evaluate our accelerator and scheduling policy on the Xilinx KU115 FPGA platform. The intermediate data transfer can be reduced by more than 90% on the VGG-D CNN model with the cross-layer strategy. Thus, the performance of our hardware accelerator reaches 1700GOP/s on the classification model VGG-D. We also implement a framework for object detection algorithms, which achieves 2.3× and 50× in energy efficiency compared with GPU and CPU, respectively. Compared with floating-point algorithms, the accuracy of the fixed-point detection algorithms only drops by less than 1%.
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Year | DOI | Venue |
|---|---|---|
2018 | 10.1145/3283452 | TRETS |
Keywords | Field | DocType |
CNN, FPGA, image object detection | Object detection,Computer science,Scheduling (computing),Parallel computing,Field-programmable gate array,Gate array,Hardware acceleration,Loop unrolling,Computer engineering,Hardware architecture,Speedup | Journal |
Volume | Issue | ISSN |
11 | 3 | 1936-7406 |
Citations | PageRank | References |
5 | 0.49 | 26 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jincheng Yu | 1 | 315 | 19.49 |
| Guangjun Ge | 2 | 7 | 3.58 |
| Yiming Hu | 3 | 639 | 44.91 |
| Xuefei Ning | 4 | 25 | 6.37 |
| Jiantao Qiu | 5 | 307 | 16.48 |
| Kaiyuan Guo | 6 | 332 | 19.19 |
| Yu Wang | 7 | 2279 | 211.60 |
| Huazhong Yang | 8 | 2239 | 214.90 |