Name
Abstract | ||
|---|---|---|
Three-dimensional Networks-on-Chip (3D-NoC) have emerged as an effective solution to the scalability and latency issues in modern complex System-On-Chips. Through-Silicon Via (TSV) is usually adopted as a viable technology enabling vertical connection among NoC layers. However, TSV-based architectures typically exhibit high vulnerability to transient and permanent faults, calling for robust routing solutions capable of sustaining operation under unpredictable failure patterns. In this paper, we introduce a complete routing solution that guarantees 100% packet delivery under an unconstrained set of runtime and permanent vertical link failures. This scheme features a baseline fully-connected low-latency deadlock-free routing algorithm, and a runtime mechanism to dynamically and progressively reconfigure the network without any packet loss. Simulation results demonstrate the effectiveness of our approach in terms of performance and reliability when compared with the state-of-the-art. Furthermore, the hardware synthesis performed using commercial 28nm technology library shows a reasonable area and power overhead with respect to the non-fault-tolerant baseline. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/DFT.2018.8602971 | 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) |
Keywords | Field | DocType |
Fault-tolerant routing algorithm,3D Networks-On-Chip,TSV failure,partially connected 3D-NoC | Computer science,Latency (engineering),Network packet,Packet loss,Computer network,Real-time computing,Fault tolerance,Elevator,Hardware synthesis,Routing algorithm,Scalability | Conference |
ISSN | ISBN | Citations |
1550-5774 | 978-1-5386-8399-6 | 0 |
PageRank | References | Authors |
0.34 | 10 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alexandre Coelho | 1 | 0 | 0.34 |
| Amir Charif | 2 | 6 | 1.86 |
| Nacer-Eddine Zergainoh | 3 | 129 | 19.39 |
| Raoul Velazco | 4 | 124 | 19.48 |