Name
Abstract | ||
|---|---|---|
In view of potential risks of piracy and malicious manipulation of complex integrated circuits built in technologies of 45 nm and less, there is an increasing need for an effective and efficient process of reverse engineering. This paper provides an overview of the current process and details on a new tool for the acquisition and synthesis of large area images and the extraction of a layout. For the first time the error between the generated layout and the known drawn GDS will be compared quantitatively as a figure of merit (FOM). From this layout a circuit graph of an ECC encryption and the partitioning in circuit blocks will be extracted.
|
Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3287624.3288738 | ASP-DAC |
Keywords | Field | DocType |
chip scanning, image processing, netlist extraction, reverse engineering | Computer science,Flow (psychology),Reverse engineering,Circuit extraction,Image processing,Electronic engineering,Encryption,Figure of merit,Integrated circuit,Circuit graph | Conference |
Citations | PageRank | References |
2 | 0.41 | 2 |
Authors | ||
10 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bernhard Lippmann | 1 | 2 | 0.75 |
| Michael Werner | 2 | 45 | 12.74 |
| Niklas Unverricht | 3 | 2 | 0.41 |
| Aayush Singla | 4 | 2 | 0.41 |
| Peter Egger | 5 | 3 | 0.81 |
| Anja Dübotzky | 6 | 2 | 0.41 |
| Horst Gieser | 7 | 10 | 3.34 |
| Martin Rasche | 8 | 2 | 0.41 |
| Oliver Kellermann | 9 | 2 | 0.41 |
| H. Graeb | 10 | 126 | 14.24 |