Name
Abstract | ||
|---|---|---|
Concerns exist that the reliability of chips is worsening because of downscaling technology. Among various reliability challenges, device aging is a dominant concern because it degrades circuit performance over time. Traditionally, runtime monitoring approaches are proposed to estimate aging effects. However, such techniques tend to predict and monitor delay degradation status for circuit mitigation measures rather than the health condition of the chip. In this paper, we propose an aging-aware chip health prediction methodology that adapts to workload conditions and process, supply voltage, and temperature variations. Our prediction methodology adopts an innovative on-chip delay monitoring strategy by tracing representative aging-aware delay behavior. The delay behavior is then fed into a machine learning engine to predict the age of the tested chips. Experimental results indicate that our strategy can obtain 97.40% accuracy with 4.14% area overhead on average. To the authors' knowledge, this is the first method that accurately predicts current chip age and provides information regarding future chip health.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3287624.3287687 | ASP-DAC |
Keywords | Field | DocType |
aging, and temperature (PVT) variation, bias-temperature instability, chip health prediction, process, support vector machine (SVM), voltage, workload | Downscaling,Computer science,Workload,Voltage,Real-time computing,Chip,Circuit performance,Reliability engineering,Tracing | Conference |
Citations | PageRank | References |
0 | 0.34 | 15 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yun-Ting Wang | 1 | 41 | 6.03 |
| Kai-Chiang Wu | 2 | 113 | 13.98 |
| Chung-Han Chou | 3 | 39 | 3.73 |
| Shih-Chieh Chang | 4 | 314 | 28.64 |