Name
Title | ||
|---|---|---|
A 81nW Error Amplifier Design for Ultra Low Leakage Retention Mode Operation of 4Mb SRAM Array in 40nm LSTP Technology |
Abstract | ||
|---|---|---|
In advanced technology nodes, static power consumption dominates system power in applications that do not operate at high frequency. SRAM leakage is a major component of static power consumption of a SOC. In this paper, we propose a 81nW ultra low power error amplifier to control retention leakage of 4Mb SRAM array. The overall memory subsystem leakage power reduces by 50% from no retention case and 33% from the conventional retention solution at TT (25°C). At FNSP (140°C) leakage power reduces by 75% from no retention & 69% from conventional solution. Monte Carlo analysis shows the 3σ variations are within guard band limits. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/SOCC.2018.8618569 | 2018 31st IEEE International System-on-Chip Conference (SOCC) |
Keywords | Field | DocType |
SRAM,Data Retention Voltage (DRV),Leakage,Memories,Low Power Design,Sub-threshold leakage,Low Standby Power (LSTP),System On Chip (SOC) | Monte Carlo method,Leakage (electronics),Error amplifier,Static random-access memory,Guard band,Transistor,Low leakage,Materials science,Electrical engineering,Power consumption | Conference |
ISSN | ISBN | Citations |
2164-1676 | 978-1-5386-1492-1 | 0 |
PageRank | References | Authors |
0.34 | 2 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ankush Mamgain | 1 | 0 | 0.34 |
| Anuj Grover | 2 | 10 | 6.49 |