Title | ||
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Reconfigurable Clock Generator with Wide Frequency Range and Single-Cycle Phase and Frequency Switching |
Abstract | ||
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Reconfigurable clock generators are critical for future heterogeneous VLSI systems. Often, system clock frequency is adapted to various working conditions, in order to improve performance under limited power budget. We propose a multiphase clock generator with reconfigurable phase spacing that allows adaptation to both phase and frequency, with fine resolution, of the synthesized clock. The phase spacing provides the base time unit to synthesize individual clock periods. The clock synthesis logic consists of a simple programmable shift register that generates individual clock periods with fine granularity and reduces the logic depth and delay, compared to previous Direct Period Synthesis (DPS) methods. The clock generator is implemented in 15 nm FinFET technology. The synthesized frequency can range between 1.57 to 13 GHz, with power consumption ranging from 0.7 to 3 mW. The frequency switching is achieved within one clock cycle, and the phase and period can be adapted with a theoretical resolution of 1 ps; however, the period jitter, which is less than 1ps in our design, limits the practical resolution to 1.5 ps. |
Year | DOI | Venue |
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2018 | 10.1109/SOCC.2018.8618532 | 2018 31st IEEE International System-on-Chip Conference (SOCC) |
Keywords | Field | DocType |
Adaptive clock,Direct Period Synthesis (DPS),multiphase clock,voltage droop,reconfigurable clock | Power budget,Clock generator,Shift register,Computer science,Frequency-division multiplexing,Electronic engineering,Ranging,System time,Jitter,Cycles per instruction | Conference |
ISSN | ISBN | Citations |
2164-1676 | 978-1-5386-1492-1 | 0 |
PageRank | References | Authors |
0.34 | 0 | 2 |
Name | Order | Citations | PageRank |
---|---|---|---|
Keyvan Ramezanpour | 1 | 2 | 1.75 |
Paul Ampadu | 2 | 285 | 28.55 |