Name
Title | ||
|---|---|---|
Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering. |
Abstract | ||
|---|---|---|
Galois field (GF) arithmetic circuits find numerous applications in communications, signal processing, and security engineering. Formal verification techniques of GF circuits are scarce and limited to circuits with known bit positions of the primary inputs and outputs. They also require knowledge of the irreducible polynomial P(x), which affects final hardware implementation. This paper presents a... |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/TCAD.2018.2808457 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
Logic gates,Reverse engineering,Hardware,Parallel processing,Galois fields,Integrated circuit modeling | Journal | 38 |
Issue | ISSN | Citations |
2 | 0278-0070 | 1 |
PageRank | References | Authors |
0.37 | 0 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cunxi Yu | 1 | 98 | 9.64 |
| Maciej J. Ciesielski | 2 | 629 | 74.80 |