Name
Abstract | ||
|---|---|---|
This is the extended summary of the PhD thesis on new test point insertion techniques. The thesis provides a comprehensive study of innovative DFT schemes going far beyond traditional logic BIST-based applications of test points. The proposed methods visibly decrease pattern counts, reduce test generation and test application times, and increase test coverage by means of algorithms capable of identifying and resolving conflicts between circuit's internal signals. In particular, it is shown that new test points provide, on the average, 2×-3× increase in test compression for stuck-at, transition and cell-aware patterns. Furthermore, it is demonstrated that test-point-centric DFT logic can be successfully used to lock a circuit or hide its functionality. As a result, this approach improves the overall hardware security against reverse engineering, IC cloning, and IP theft. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TEST.2018.8624900 | 2018 IEEE International Test Conference (ITC) |
Keywords | Field | DocType |
logic BIST-based applications,DFT schemes,test compression,test generation,test point insertion techniques,test-point-centric DFT logic | Code coverage,Hardware security module,Computer science,Lock (computer science),Reverse engineering,Term logic,Electronic engineering,Test compression,Computer engineering,Test point insertion | Conference |
ISSN | ISBN | Citations |
1089-3539 | 978-1-5386-8383-5 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Janusz Rajski | 1 | 2460 | 201.28 |
| Jerzy Tyszer | 2 | 838 | 74.98 |
| Justyna Zawada | 3 | 20 | 3.48 |