Paper Info
Title
Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines
Abstract
DRAM latency is a major bottleneck for many applications in modern computing systems. In this work, we rigorously characterize the effects of reducing DRAM access latency on 282 state-of-the-art LPDDR4 DRAM modules. As found in prior work on older DRAM generations (DDR3), we show that regions of LPDDR4 DRAM modules can be accessed with latencies that are significantly lower than manufacturer-specified values without causing failures. We present novel data that 1) further supports the viability of such latency reduction mechanisms and 2) exposes a variety of new cases in which access latencies can be effectively reduced. Using our observations, we propose a new low-cost mechanism, Solar-DRAM, that 1) identifies failure-prone regions of DRAM at reduced latency and 2) robustly reduces average DRAM access latency while maintaining data correctness, by issuing DRAM requests with reduced access latencies to non-failure-prone DRAM regions. We evaluate Solar-DRAM on a wide variety of multi-core workloads and show that for 4-core homogeneous workloads, Solar-DRAM provides an average (maximum) system performance improvement of 4.31% (10.87%) compared to using the default fixed DRAM access latency.
Year
DOI
Venue
2018
10.1109/ICCD.2018.00051
2018 IEEE 36th International Conference on Computer Design (ICCD)
Keywords
Field
DocType
DRAM-Latency,DRAM-Characterization,Process-Variation,LPDDR4,Memory,Memory-Controllers
Dram,Bottleneck,Computer science,Homogeneous,Latency (engineering),Parallel computing,Correctness,Process variation,Computing systems,Embedded system,Performance improvement
Conference
ISSN
ISBN
Citations 
1063-6404
978-1-5386-8478-8
6
PageRank 
References 
Authors
0.36
31
4
Name
Order
Citations
PageRank
Jeremie Kim126313.68
Minesh Patel22049.82
Hasan Hassan335217.76
Onur Mutlu49446357.40