Name
Abstract | ||
|---|---|---|
In this contribution, we provide insights on the practical feasibility, effectiveness, and validation of a software-based fault-tolerance architecture we developed for use aboard small satellites. We exploit thread-level coarse-grain lockstep to facilitate forward-error-correction and assures computational correctness on an FPGA-based MPSoC. It can be implemented using standard open-source and FPGA design tools, requires only standard COTS components, and is processor architecture and operating system agnostic. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/PRDC.2018.00043 | 2018 IEEE 23rd Pacific Rim International Symposium on Dependable Computing (PRDC) |
Keywords | Field | DocType |
Computer architecture,Field programmable gate arrays,Circuit faults,Fault tolerance,Fault tolerant systems,Hardware,Space vehicles | Computer science,Lockstep,Correctness,Field-programmable gate array,Exploit,Fault tolerance,Software,MPSoC,Microarchitecture,Embedded system,Distributed computing | Conference |
ISSN | ISBN | Citations |
1555-094X | 978-1-5386-5700-3 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christian M. Fuchs | 1 | 1 | 1.72 |
| Nadia M. Murillo | 2 | 1 | 1.05 |
| Aske Plaat | 3 | 524 | 72.18 |
| Erik van der Kouwe | 4 | 58 | 9.55 |
| Daniel Harsono | 5 | 0 | 0.68 |
| Peng Wang | 6 | 385 | 106.03 |