Name
Abstract | ||
|---|---|---|
We present a post-routing model that relates both logic and routing architecture parameters to wirelength for a homogeneous FPGA architecture. Our model relies on Rent’s parameter generated from the pre-technology mapped netlist rather than post-placement netlist making it independent from optimization goal of the technology-mapping, clustering and placement stages of the FPGA CAD flow. We achieve an average mean absolute percentage error (MAPE) of 36% relative to the Verilog-to-Routing (VTR) based wire-length analysis using MCNC and VTR benchmarks, while state-of-the-art approach achieves a MAPE of 57%. This work forms the basis for implementing post-routing delay, routability and power models, since each can be expressed as a function of net length. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/RECONFIG.2018.8641724 | 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig) |
Keywords | Field | DocType |
Analytical Model,FPGA,Post-routing Wire-length | Mean absolute percentage error,Routing architecture,Netlist,Homogeneous,Computer science,Parallel computing,Field-programmable gate array,Fpga architecture,Cluster analysis,Cad flow | Conference |
ISSN | ISBN | Citations |
2325-6532 | 978-1-7281-1968-7 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Arpit Soni | 1 | 0 | 0.34 |
| Yoon Kah Leow | 2 | 3 | 2.10 |
| Ali Akoglu | 3 | 157 | 29.40 |