Paper Info
Title
An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing
Abstract
The emergence of nanophotonic devices has enabled to design integrated optical circuits for ultra-high speed on-chip signal processing. This paper proposes an optical implementation of an approximate parallel multiplier for two n-bit integers. The key to ultra-high speed processing is to reduce the number of OptoElectric (OE) converters on a critical path since the OE converters dominantly determine the operating speed of the multiplier. For any n, the proposed approximate multiplier has only three OE converters on a critical path with a deterministic error (11% at the worst case). On the other hand, the number of the counterparts of the conventional parallel multiplier increases as <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$n$</tex> increases, which implies that the proposed multiplier with large <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$n$</tex> exhibits much better operating speed than the conventional optical parallel multiplier. Numerical evaluation for n = 16 shows that the proposed multiplier exhibits a 106 ps latency which is 49% less than that of the conventional optical multiplier.
Year
DOI
Venue
2018
10.1109/ICRC.2018.8638614
2018 IEEE International Conference on Rebooting Computing (ICRC)
Keywords
Field
DocType
Optical signal processing,Adaptive optics,Optical switches,Adders,Optical fibers,Optical design
Topology,Signal processing,Adder,Optical switch,Computer science,Operating speed,Converters,Multiplier (economics),Critical path method,Electronic circuit
Conference
ISBN
Citations 
PageRank 
978-1-5386-9170-0
0
0.34
References 
Authors
0
5
Name
Order
Citations
PageRank
Jun Shiomi101.35
Tohru Ishihara271987.96
Hidetoshi Onodera3455105.29
Akihiko Shinya495.93
Masaya Notomi599.31