Name
Abstract | ||
|---|---|---|
Editor’s note: Microfluidic very large scale integration (mVLSI) plays a crucial role for designing point-of-care systems. This article analyzes the impact of manufacturing and physical defects across all layers of the bio-chip architectures and proposes a graph theory-inspired formulation for maximizing the fault coverage through test point insertion. This represents a worthwhile contribution to design-for-testability of mVLSI systems. —Paul Bogdan, University of Southern California |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/MDAT.2018.2873448 | IEEE Design & Test |
Keywords | Field | DocType |
Valves,Circuit faults,Logic gates,System-on-chip,Logic circuits,Process control | Design for testing,Graph,Logic gate,Biochip,System on a chip,Fault coverage,Computer science,Process control,Computer engineering,Very-large-scale integration,Embedded system | Journal |
Volume | Issue | ISSN |
36 | 1 | 2168-2356 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seetal Potluri | 1 | 15 | 8.46 |
| Paul Pop | 2 | 62 | 9.23 |
| Jan Madsen | 3 | 576 | 56.90 |