Paper Info
Title
A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach
Abstract
Near threshold computing (NTC) has significant role in reducing the energy consumption of modern very large scale integrated circuits designs. However, NTC designs suffer from functional failures and performance loss. Understanding the characteristics of the functional failures and variability effects is of decisive importance in order to mitigate them, and get the utmost NTC benefits. This paper presents a comprehensive cross-layer reliability analysis framework to assess the effect of soft error, aging, and process variation in the operation of near threshold voltage caches. The objective is to quantify the reliability of different SRAM designs, evaluate voltage scaling potential of caches, and to find a reliability-performance optimal cache organization for an NTC microprocessor. In this paper, the soft error rate (SER) and static noise margin (SNM) of 6T and 8T SRAM cells and their dependencies on aging and process variation are investigated by considering device, circuit, and architecture level analysis. Their experimental results show that in NTC, process variation and aging-induced SNM degradation is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.5{\boldsymbol \times }$ </tex-math></inline-formula> higher than in the super threshold domain while SER is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8{\boldsymbol \times }$ </tex-math></inline-formula> higher. At NTC, the use of 8T instead of 6T SRAM cells can reduce the system-level SNM and SER by 14% and 22%, respectively. Besides, we observe that we can find the right balance between performance and reliability by using an appropriate cache organization at NTC which is different from the super threshold.
Year
DOI
Venue
2019
10.1109/TCAD.2018.2818691
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Keywords
Field
DocType
SRAM cells,Integrated circuit reliability,Threshold voltage,Reliability engineering,Aging,Transistors
Soft error,Cache,Computer science,Voltage,Microprocessor,Static random-access memory,Electronic engineering,Process variation,Energy consumption,Threshold voltage
Journal
Volume
Issue
ISSN
38
3
0278-0070
Citations 
PageRank 
References 
0
0.34
0
Authors
3
Name
Order
Citations
PageRank
Anteneh Gebregiorgis1224.91
Rajendra Bishnoi213219.64
Mehdi B. Tahoori31537163.44