Title
A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS
Abstract
This paper presents a four-level pulse amplitude modulation (PAM4) quarter-rate receiver that efficiently compensates for moderate channel loss in a robust manner through background adaptation of the receiver thresholds and equalization taps. The front-end utilizes an input single-stage continuous-time linear equalizer (CTLE) to boost the main cursor and relax the pre-cursor cancellation requirement, requiring only a 2-tap pre-cursor feed-forward equalizer (FFE) on the transmitter side. A 2-tap decision feedback equalizer (DFE) follows that includes one finite impulse response (FIR) tap and one infinite impulse response (IIR) tap to cancel first post-cursor and long-tail inter-symbol interference (ISI), respectively. In addition to the per-slice main three data samplers, a single error sampler is utilized for background threshold control and an edge-based sampler performs both phase-locked loop (PLL)-based clock and data recovery (CDR) phase detection and generates information for background DFE tap adaptation. Fabricated in general purpose (GP) 65-nm CMOS, the 56-Gb/s receiver achieves 4.63 mW/Gb/s and compensates for up to 20.8-dB loss at a bit error rate (BER) < 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> when operated with a 2-tap FFE transmitter.
Year
DOI
Venue
2019
10.1109/JSSC.2018.2881278
IEEE Journal of Solid-State Circuits
Keywords
Field
DocType
Receivers,Decision feedback equalizers,Finite impulse response filters,Clocks,Transmitters,Bit error rate
Phase-locked loop,Transmitter,Equalization (audio),Control theory,Computer science,Infinite impulse response,Electronic engineering,Phase detector,Finite impulse response,Pulse-amplitude modulation,Bit error rate
Journal
Volume
Issue
ISSN
54
3
0018-9200
Citations 
PageRank 
References 
8
0.69
0
Authors
10