Author Info
Name
Affiliation
Papers
SAMUEL PALERMO
Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA
16
Collaborators
Citations 
PageRank 
66
46
7.88
Referers 
Referees 
References 
210
358
64
Search Limit
100358
Title
Citations
PageRank
Year
A 12.5 Gb/s 1.38 mW Inverter-Based Optical Receiver in 28 nm CMOS00.342022
Automated Tuning for Silicon Photonic Filters00.342022
Recurrent Neural Network Equalization for Wireline Communication Systems00.342022
A Power-Efficient 20-35 GHz MZM Driver with Programmable Linearizer in 28nm CMOS00.342021
A 40Gb/s Linear Redriver with Multi-Band Equalization in 130nm SiGe BiCMOS00.342021
A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS80.692019
A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization.40.452016
25Gb/s hybrid-integrated silicon photonic receiver with microring wavelength stabilization30.422015
Energy efficiency comparisons of NRZ and PAM4 modulation for ring-resonator-based silicon photonic links20.442015
A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS111.322015
A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS20.412014
An 8–16 Gb/s, 0.65–1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning50.532014
A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O Transceiver in 65 nm CMOS.10.382013
A 6-Gbit/s Hybrid Voltage-Mode Transmitter With Current-Mode Equalization in 90-nm CMOS.40.542012
0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking.60.682012
Low-Power 8gb/S Near-Threshold Serial Link Receivers Using Super-Harmonic Injection Locking In 65nm Cmos00.342011