Paper Info
Title
Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding
Abstract
The Display Stream Compression (DSC) standard enables visually-lossless video compression with a much lower hardware cost than H.264 and HEVC albeit with a lower level of compression. We present the first published DSC encoder architectures—including a Single Slice architecture which supports one slice per line encoding and a Slice Interleaving architecture which supports one or more slices per line. Seven designs that fully support the DSC v1.2a standard have been implemented and synthesized in a 28 nm CMOS standard cell library. The designs are able to perform real-time encoding at frame rates up to 35–40 frames per second (fps) for 8K UHD $(7680\times4320)$, 140–160 fps for 4K UHD $(3840\times2160)$, and 560– 642 fps for 1080 p $(1920\times1080)$ video in 4:4:4 mode. In native 4:2:2 and 4:2:0 modes, frame rates are doubled to 70–80 fps, 280–320 fps and 1120–1284 fps for 8K UHD, 4K UHD and 1080p, respectively. The designs require 194–433 K minimum-sized NAND2 equivalent gates and main memory of 31.9–68.5 KB to support 8K UHD.
Year
DOI
Venue
2018
10.1109/ACSSC.2018.8645369
2018 52nd Asilomar Conference on Signals, Systems, and Computers
Keywords
Field
DocType
Encoding,UHDTV,Computer architecture,Multiplexing,Streaming media,Registers,Hardware
1080p,Computer science,Electronic engineering,Standard cell,Encoder,Frame rate,Data compression,Computer hardware,Multiplexing,Interleaving,Encoding (memory)
Conference
ISSN
ISBN
Citations 
1058-6393
978-1-5386-9218-9
0
PageRank 
References 
Authors
0.34
0
4
Name
Order
Citations
PageRank
Shifu Wu100.68
Snehlata Gutgutia200.34
Massimo Alioto370688.98
Bevan M. Baas429527.78