Paper Info
Title
Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor
Abstract
The modern era of Internet-of-Things (IoT) is naturally imposing a tight area/runtime constraint on the computing kernels. Security kernels, as part of the standardized protocols as well as custom defense techniques, are among the most common tasks executed on every digital device. Therefore, low area cost and high performance implementation of security kernels is an important goal of current system designers. In this paper, we revisit the state-of-the-art implementations of SHA-256, a standardized security primitive for authentication and propose novel optimizations. Our optimizations, based on architectural folding and 4-2 adder compressor, are geared toward both lightweight and high performance implementations. Detailed experiments of our optimized architecture on different FPGA fabrics clearly demonstrate their benefits. Our presented design point successfully attained the highest hardware efficiency (throughput/area) figures among the published literature so far.
Year
DOI
Venue
2018
10.1109/VLSI-SoC.2018.8644825
2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Keywords
Field
DocType
Adders,Hardware,Computer architecture,Throughput,Optimization,Security,Resource management
Resource management,Architecture,Authentication,Adder,Computer science,Field-programmable gate array,Implementation,Gas compressor,Throughput,Embedded system
Conference
ISSN
ISBN
Citations 
2324-8432
978-1-5386-4756-1
0
PageRank 
References 
Authors
0.34
0
3
Name
Order
Citations
PageRank
wong ming ming102.03
Vikramkumar Pudi2175.96
Anupam Chattopadhyay331862.76