| Will You Cross the Threshold for Me? Generic Side-Channel Assisted Chosen-Ciphertext Attacks on NTRU-based KEMs. | 0 | 0.34 | 2022 |
| Feeding Three Birds With One Scone - A Generic Duplication Based Countermeasure To Fault Attacks. | 0 | 0.34 | 2021 |
| Three Input Exclusive-OR Gate Support For Boyar-Peralta's Algorithm (Extended Version). | 0 | 0.34 | 2021 |
| Three Input Exclusive-OR Gate Support for Boyar-Peralta's Algorithm. | 0 | 0.34 | 2021 |
| Practical Side-Channel and Fault Attacks on Lattice-Based Cryptography | 0 | 0.34 | 2021 |
| A Novel Duplication Based Countermeasure to Statistical Ineffective Fault Analysis. | 0 | 0.34 | 2020 |
| Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA | 1 | 0.34 | 2020 |
| Threshold Implementations Of Gift: A Trade-Off Analysis | 0 | 0.34 | 2020 |
| Towards Designing a Secure RISC-V System-on-Chip: ITUS | 0 | 0.34 | 2020 |
| Efficient Quantum Circuits for Square-Root and Inverse Square-Root | 0 | 0.34 | 2020 |
| On Configurable SCA Countermeasures Against Single Trace Attacks for the NTT - A Performance Evaluation Study over Kyber and Dilithium on the ARM Cortex-M4. | 0 | 0.34 | 2020 |
| A Coding Theoretic Approach Towards Symmetrization In Reversible Circuit Synthesis | 0 | 0.34 | 2020 |
| Re-markable - Stealing Watermarked Neural Networks Through Synthesis. | 0 | 0.34 | 2020 |
| A Brain–Computer Interface Framework Based on Compressive Sensing and Deep Learning | 0 | 0.34 | 2020 |
| Enabling Efficient Mapping of XMG-Synthesized Networks to Spintronic Hardware | 0 | 0.34 | 2020 |
| Lightweight Secure-Boot Architecture for RISC-V System-on-Chip | 2 | 0.39 | 2019 |
| SPQCop: Side-channel protected Post-Quantum Cryptoprocessor. | 0 | 0.34 | 2019 |
| Number "Not Used" Once - Practical Fault Attack on pqm4 Implementations of NIST Candidates. | 1 | 0.35 | 2019 |
| Optimizing Quantum Circuits for Modular Exponentiation | 0 | 0.34 | 2019 |
| Analysis Of The Strict Avalanche Criterion In Variants Of Arbiter-Based Physically Unclonable Functions | 2 | 0.37 | 2019 |
| RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders | 0 | 0.34 | 2019 |
| Guest Editorial Special Section on Security Challenges and Solutions With Emerging Computing Technologies | 0 | 0.34 | 2019 |
| Exploiting Determinism in Lattice-based Signatures - Practical Fault Attacks on pqm4 Implementations of NIST Candidates. | 1 | 0.35 | 2019 |
| Exploiting Determinism in Lattice-based Signatures: Practical Fault Attacks on pqm4 Implementations of NIST Candidates. | 0 | 0.34 | 2019 |
| Generic Side-channel attacks on CCA-secure lattice-based PKE and KEM schemes. | 0 | 0.34 | 2019 |
| Spintronic Device-Structure for Low-Energy XOR Logic using Domain Wall Motion | 1 | 0.37 | 2019 |
| Design and synthesis of improved reversible circuits using AIG- and MIG-based graph data structures. | 0 | 0.34 | 2019 |
| Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization. | 0 | 0.34 | 2018 |
| Crack Me If You Can: Hardware Acceleration Bridging The Gap Between Practical And Theoretical Cryptanalysis? A Survey | 0 | 0.34 | 2018 |
| CoLPUF : A Novel Configurable LFSR-based PUF | 0 | 0.34 | 2018 |
| Accelerating Hash Computations Through Efficient Instruction-Set Customisation | 2 | 0.51 | 2018 |
| On Hardware Implementation of Tang-Maitra Boolean Functions. | 0 | 0.34 | 2018 |
| A template-based technique for efficient Clifford+T-based quantum circuit implementation. | 5 | 0.63 | 2018 |
| BLIC: A Blockchain Protocol for Manufacturing and Supply Chain Management of ICS | 1 | 0.36 | 2018 |
| Side-channel Assisted Existential Forgery Attack on Dilithium - A NIST PQC candidate. | 0 | 0.34 | 2018 |
| ReRAM-based In-Memory Computation of Galois Field arithmetic | 0 | 0.34 | 2018 |
| Number "Not" Used Once - Key Recovery Fault Attacks on LWE Based Lattice Cryptographic Schemes. | 0 | 0.34 | 2018 |
| PPAP and iPPAP: PLL-Based Protection Against Physical Attacks. | 0 | 0.34 | 2018 |
| RAPPER: Ransomware Prevention via Performance Counters. | 1 | 0.35 | 2018 |
| Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor | 0 | 0.34 | 2018 |
| A Hardware-Efficient Implementation of CLOC for On-chip Authenticated Encryption | 0 | 0.34 | 2018 |
| TriviA and uTriviA: two fast and secure authenticated encryption schemes. | 0 | 0.34 | 2018 |
| Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design. | 2 | 0.38 | 2018 |
| Domain Wall Motion-based Dual-Threshold Activation Unit for Low-Power Classification of Non-Linearly Separable Functions. | 0 | 0.34 | 2018 |
| Security of autonomous vehicle as a cyber-physical system | 0 | 0.34 | 2017 |
| Automatic Test Pattern Generation for Multiple Missing Gate Faults in Reversible Circuits - Work in Progress Report. | 0 | 0.34 | 2017 |
| Efficient complementary resistive switch-based crossbar array Booth multiplier. | 2 | 0.38 | 2017 |
| RC4-AccSuite: A Hardware Acceleration Suite for RC4-Like Stream Ciphers. | 2 | 0.37 | 2017 |
| Survey of secure processors | 0 | 0.34 | 2017 |
| Depth-Optimal Quantum Circuit Placement for Arbitrary Topologies. | 3 | 0.47 | 2017 |
