Name
Abstract | ||
|---|---|---|
This paper proposes a synthesizable digital LDO that is implemented with standard-cell-based digital design flow. With inverter chains as voltage-controlled delay lines, the difference between output and reference voltages is converted into delay difference, then compared in time-domain. Since the time-domain difference is straightforwardly captured by a phase detector that consists of a D-FF, the proposed LDO does not need an analog voltage comparator, which requires careful manual design. The prototype of the proposed LDO is fabricated in 65 nm standard CMOS technology with 0.015 mm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
area occupation. The measurement results show that with 10.4 MHz internal clock the tracking response to 200 mV switching of the reference voltage is ~4.5 μs and the transient response to 5 mA change of the load current is ~6.6 μs. The quiescent current consumed by the LDO core is as low as 35.2 μA at 10 mA load current, which leads to 99.6 % current efficiency. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/VLSI-SoC.2018.8644879 | 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) |
Keywords | Field | DocType |
Inverters,Clocks,Detectors,Control systems,Pulse generation,Standards,Logic gates | Transient response,Inverter,Comparator,Computer science,Voltage reference,Voltage,CMOS,Phase detector,Electrical engineering,Low-dropout regulator | Conference |
ISSN | ISBN | Citations |
2324-8432 | 978-1-5386-4756-1 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Naoki Ojima | 1 | 1 | 1.37 |
| Toru Nakura | 2 | 92 | 31.27 |
| Tetsuya Iizuka | 3 | 92 | 33.22 |
| kunihiro asada | 4 | 273 | 78.26 |