| Fully Dynamic Discrete-Time ΔΣ ADC Using Closed-Loop Two-Stage Cascoded Floating Inverter Amplifiers | 1 | 0.35 | 2022 |
| A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW | 1 | 0.36 | 2021 |
| An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC | 1 | 0.35 | 2021 |
| A Calibration Technique For Simultaneous Estimation Of Actual Sensing Matrix Coefficients On Modulated Wideband Converters | 0 | 0.34 | 2020 |
| A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving –66dBc Worst-Case In-Band Fractional Spur | 1 | 0.40 | 2020 |
| Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing | 0 | 0.34 | 2020 |
| Theoretical Analysis of Noise Figure for Modulated Wideband Converter | 1 | 0.36 | 2020 |
| Spatial Resolution Improvement For Point Light Source Detection In Scintillator Cube Using Spad Array With Multi Pinholes | 0 | 0.34 | 2019 |
| Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field | 0 | 0.34 | 2019 |
| A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. | 0 | 0.34 | 2019 |
| A Compact Quick-Start Sub-Mw Pulse-Width-Controlled Pll With Automated Layout Synthesis Using A Place-And-Route Tool | 0 | 0.34 | 2019 |
| A 0.0053-mm<sup>2</sup> 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS | 0 | 0.34 | 2019 |
| A 140 Ghz Area-And-Power-Efficient Vco Using Frequency Doubler In 65 Nm Cmos | 0 | 0.34 | 2019 |
| A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion | 0 | 0.34 | 2018 |
| Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. | 0 | 0.34 | 2018 |
| Triangular Active Charge Injection Method For Resonant Power Supply Noise Reduction | 0 | 0.34 | 2018 |
| Noninvasive Localization of IGBT Faults by High-Sensitivity Magnetic Probe With RF Stimulation. | 0 | 0.34 | 2018 |
| Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit. | 1 | 0.36 | 2018 |
| Time-Domain Approach For Analog Circuits In Deep Sub-Micron Lsi | 2 | 0.37 | 2018 |
| A Unified Analysis Of The Signal Transfer Characteristics Of A Single-Path Fet-R-C Circuit | 0 | 0.34 | 2018 |
| Optimal Design Method Of Sub-Ranging Adc Based On Stochastic Comparator | 0 | 0.34 | 2018 |
| A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. | 0 | 0.34 | 2018 |
| Quick-Start Pulse Width Controlled Pll With Frequency And Phase Presetting | 0 | 0.34 | 2018 |
| Impulse signal generator based on current-mode excitation and transmission line resonator | 0 | 0.34 | 2017 |
| Extension of power supply impedance emulation method on ATE for multiple power domain | 0 | 0.34 | 2017 |
| Design, Analysis And Implementation Of Pulse Generator By Cmos Flipped On Glass For Low Power Uwb-Ir | 0 | 0.34 | 2017 |
| High Spatial Resolution Detection Method for Point Light Source in Scintillator. | 0 | 0.34 | 2017 |
| A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using A Delay Line Ring | 0 | 0.34 | 2017 |
| Session 4 — Modeling and measurement of mixed-signal circuits | 0 | 0.34 | 2017 |
| A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout | 0 | 0.34 | 2017 |
| A Pll Compiler From Specification To Gdsii | 0 | 0.34 | 2017 |
| A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator | 0 | 0.34 | 2017 |
| FET-R-C Circuits: A Unified Treatment-Part I: Signal Transfer Characteristics of a Single-Path | 3 | 0.44 | 2016 |
| FET-R-C Circuits: A Unified Treatment - Part I: Signal Transfer Characteristics of a Single-Path. | 3 | 0.40 | 2016 |
| FET-R-C Circuits: A Unified Treatment - Part II: Extension to Multi-Paths, Noise Figure, and Driving-Point Impedance. | 3 | 0.43 | 2016 |
| A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. | 0 | 0.34 | 2016 |
| A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse | 1 | 0.38 | 2016 |
| An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors. | 1 | 0.38 | 2016 |
| Analytical design optimization of sub-ranging ADC based on stochastic comparator. | 0 | 0.34 | 2016 |
| A Near-Field Magnetic Sensing System With High-Spatial Resolution and Application for Security of Cryptographic LSIs | 0 | 0.34 | 2015 |
| An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors | 0 | 0.34 | 2015 |
| A calibration-free time difference accumulator using two pulses propagating on a single buffer ring | 0 | 0.34 | 2015 |
| Session 3 — Optical interconnect and reliability enhancement techniques | 0 | 0.34 | 2015 |
| F1: High-speed interleaved ADCs | 0 | 0.34 | 2015 |
| Session 12 — Tutorial — beyond CMOS: Large area electronics-concepts and prospects | 0 | 0.34 | 2015 |
| Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator | 1 | 0.35 | 2015 |
| High-resolution measurement of magnetic field generated from cryptographic LSIs | 1 | 0.36 | 2014 |
| A Structured Routing Architecture For Practical Application Of Character Projection Method In Electron-Beam Direct Writing | 0 | 0.34 | 2014 |
| Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration. | 0 | 0.34 | 2014 |
| A Pulse Width controlled PLL and its automated design flow | 3 | 0.59 | 2013 |
