Paper Info
Title
Low-Power Null Convention Logic Multiplier Design Based On Gate Diffusion Input Technique
Abstract
The increasing power consumption in the synchronous circuits is the major concern in the semiconductor industry. The major contributor to this power consumption is the clock generator and the clock distribution. This problem can be addressed by using the asynchronous circuits. Null Convention Logic (NCL) is one of the most commonly known delay insensitive approach for designing asynchronous designs. However, realizing the NCL circuits using the commonly used complementary metal oxide semiconductor (CMOS) technique is said to increase the area and the power consumption. The low power design technique known as Gate Diffusion Input (GDI) can be used for implementing the NCL circuits to reduce both the area and the power. Application of the external input to the sources of the pMOS and nMOS transistors, allows to reduces the area and the dynamic switching. Thus, decreasing the transistor count and the power. The proposed GDI NCL technique is used for designing the 4-bit un-pipelined NCL multiplier. The design was realized and simulated in gpdk045 Cadence Virtuoso. In comparison to the CMOS model, the GDI model shows 21.6 % in transistor count and the dynamic power is reduced by 13.7 %.
Year
DOI
Venue
2018
10.1109/ISOCC.2018.8649885
2018 International SoC Design Conference (ISOCC)
Keywords
Field
DocType
Logic gates,Semiconductor device modeling,Transistors,Power demand,Clocks,Integrated circuit modeling,Threshold voltage
Transistor count,Clock generator,Logic gate,NMOS logic,Computer science,Electronic engineering,CMOS,Dynamic demand,Transistor,Low-power electronics
Conference
ISSN
ISBN
Citations 
2163-9612
978-1-5386-7960-9
0
PageRank 
References 
Authors
0.34
0
4
Name
Order
Citations
PageRank
Prashanthi Metku102.70
Kyung Ki Kim29921.62
Yong-Bin Kim3227.14
Minsu Choi415627.63