Title
LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives
Abstract
The reliability of non-volatile NAND flash memories is reaching critical levels for traditional error detection and correction. Therefore, to ensure data trustworthiness in nowadays NAND flash-based Solid State Drives, it is essential to exploit powerful correction algorithms such as the Low Density Parity Check. However, the burdens of this approach materialize in a disk performance reduction. In this work a standard decoding approach is compared with an optimized solution exploiting hardware resources available in NAND flash chips. The simulation results on 2X, 1X and mid-1X MLC and TLC NAND flashbased Solid State Drives in terms of disk bandwidth, average latency, and Quality of Service favor the adoption of the presented solution in different host scenarios and realistic workloads. The proposed solution is particularly effective when high error correction interventions and read- or write-intensive workloads are considered.
Year
DOI
Venue
2019
10.1109/TETC.2017.2688079
IEEE Transactions on Emerging Topics in Computing
Keywords
Field
DocType
High definition video,Parity check codes,Data transfer,Decoding,Error correction codes,Computer architecture,Engines
High-definition video,Data transmission,Low-density parity-check code,Computer science,Quality of service,Real-time computing,NAND gate,Error detection and correction,Bandwidth (signal processing),Decoding methods,Computer hardware,Embedded system
Journal
Volume
Issue
ISSN
7
3
2168-6750
Citations 
PageRank 
References 
1
0.37
0
Authors
5
Name
Order
Citations
PageRank
Lorenzo Zuolo182.35
Cristian Zambelli2369.05
alessia marelli3203.64
Rino Micheloni46912.85
P. Olivo534258.07