Name
Title | ||
|---|---|---|
Embedded FFT hardware algorithm development using automated bi-dimensional scalable folding |
Abstract | ||
|---|---|---|
This paper presents an original and unique embedded FFT hardware algorithm development process based on a systematic and scalable procedure for generating permutation-based address patterns for any power-of-2 transform size algorithm and any folding factor in a Kronecker Pease FFT hardware implementation. This is coupled by a procedure to perform automatic code generation of Kronecker FFT cores. The paper presents important results about twiddle address pattern generation and data switch multiplexing techniques. The paper also presents analyses and comparisons of the architecture design performance in terms of clock latency, accuracy, and hardware resources for benchmarking implementation efforts performed on the Xilinx Virtex-7 FPGA. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/MWSCAS.2017.8052965 | Midwest Symposium on Circuits and Systems Conference Proceedings |
Field | DocType | ISSN |
Kronecker delta,Computer science,Permutation,Parallel computing,Field-programmable gate array,Electronic engineering,Code generation,Network switch,Fast Fourier transform,Multiplexing,Scalability | Conference | 1548-3746 |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Felipe Minotta | 1 | 0 | 0.34 |
| Manuel Jiménez | 2 | 20 | 6.31 |
| Domingo Rodríguez | 3 | 20 | 8.03 |