Paper Info
Title
A content addressable memory with multi-Vdd scheme for low power tunable operation
Abstract
This paper reports on a content addressable memory (CAM) employing a multi-Vdd scheme for low power pattern recognition applications. The complete design, simulation and testing of the chip is presented along with an exploration of the multi-Vdd design space. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the delay range by 2.4 times and consumes 25.3% less power when compared to a conventional single-Vdd design operating over the same voltage range. Measurement results from a 246 kb test chip fabricated in 130nm Global Foundries Low Power CMOS technology are presented to validate the model and analysis.
Year
DOI
Venue
2017
10.1109/MWSCAS.2017.8052945
Midwest Symposium on Circuits and Systems Conference Proceedings
Keywords
Field
DocType
Content addressable memory (CAM),TCAM,multi Vdd,multi supply,low power,associative memory,tunable operation
Design space,Content-addressable memory,Propagation delay,Computer science,Operating point,Voltage,Electronic engineering,Chip,CMOS,Power demand
Conference
ISSN
Citations 
PageRank 
1548-3746
0
0.34
References 
Authors
6
9
Name
Order
Citations
PageRank
Siddhartha Joshi122.10
Dawei Li272.23
Seda Ogrenci Memik300.68
G. Deptuch401.35
James Hoff521.09
Sergo Jindariani6172.36
Tiehui Liu720.75
Jamieson Olsen820.75
Nhan Tran9186.08