Name
Abstract | ||
|---|---|---|
Multilevel cell (MLC) states with lower threshold voltage endure less cell damage, lower retention error, and less current consumption. Based on these characteristics, it is opportunistic to strengthen MLC flash by introducing bit-flipping that reshapes state proportions on MLC pages. In this paper, we present a holistic study of bit-flipping schemes upon MLC flash in theory and practice. Specifically, we systematically investigate effective bit-flipping schemes and propose four new schemes on manipulating MLC states. We further design a generic implementation framework, named MLC bit-flipping framework, to implement bit-flipping schemes within solid state drives controllers, nicely integrating with existing system-level optimizations to further improve overall performance. The experimental results demonstrate that our proposed bit-flipping schemes standalone can reduce up to 28% cell damages and 53% retention errors. Our circuit-level simulation manifests that the bit-flipping latency on a page is less than 4
<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>
when using 8K logic gates. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/tcad.2018.2818693 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
Erbium,Writing,Threshold voltage,Reliability,Degradation,Standards | Logic gate,Latency (engineering),Computer science,Electronic engineering,Current consumption,Threshold voltage,Solid-state | Journal |
Volume | Issue | ISSN |
38 | 4 | 0278-0070 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wenhui Zhang | 1 | 292 | 43.28 |
| Qiang Cao | 2 | 593 | 57.50 |
| Zhonghai Lu | 3 | 1063 | 100.12 |