Paper Info
Title
Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs
Abstract
Deep learning workloads, such as convolutional neural networks (CNNs) are important due to increasingly demanding high-performance hardware acceleration. One distinguishing feature of a deep learning workload is that it is inherently resilient to small numerical errors and thus works very well with low precision hardware. We propose a novel method called double multiply-and-accumulate (MAC) to theoretically double the computation rate of CNN accelerators by packing two MAC operations into one digital signal processing block of off-the-shelf field-programmable gate arrays (FPGAs). We overcame several technical challenges by exploiting the mode of operation in the CNN accelerator. We have validated our method through FPGA synthesis and Verilog simulation, and evaluated our method by applying it to the state-of-the-art CNN accelerator. The double MAC approach used can double the computation throughput of a CNN layer. On the network level (all convolution layers combined), the performance improvement varies depending on the CNN application and FPGA size, from 14% to more than 80% over a highly optimized state-of-the-art accelerator solution, without sacrificing the output quality significantly.
Year
DOI
Venue
2019
10.1109/tcad.2018.2824280
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Keywords
Field
DocType
Field programmable gate arrays,Convolution,Hardware,Table lookup,Throughput,Accelerator architectures
Digital signal processing,Convolutional neural network,Computer science,Field-programmable gate array,Electronic engineering,Hardware acceleration,Artificial intelligence,Boosting (machine learning),Verilog,Deep learning,Computer hardware,Performance improvement
Journal
Volume
Issue
ISSN
38
5
0278-0070
Citations 
PageRank 
References 
4
0.48
0
Authors
4
Name
Order
Citations
PageRank
Sugil Lee182.60
Daewoo Kim281.24
Dong Nguyen368249.92
Jongeun Lee442933.71