Name
Abstract | ||
|---|---|---|
This paper presents a novel and effective logic synthesis flow able to identify threshold logic functions during the technology mapping process. It provides more efficient logic covering, exploring also redundant cuts. Moreover, the proposed design flow takes into account different circuit area estimations, such as the sum of input weights and threshold values, the gate fanin and the number of threshold logic gates. As a result, the mapped circuits present a reduction up to 47% and 67% in area and logic depth, respectively, in comparison to the most recent related approaches. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/tcad.2018.2834434 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
Logic gates,Estimation,Delays,Boolean functions,Tools,Field programmable gate arrays,Digital circuits | Boolean function,Logic synthesis,Logic gate,Digital electronics,Computer science,Field-programmable gate array,Design flow,Electronic engineering,Electronic circuit,AND gate | Journal |
Volume | Issue | ISSN |
38 | 5 | 0278-0070 |
Citations | PageRank | References |
1 | 0.37 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Augusto Neutzling | 1 | 20 | 2.93 |
| Jody Maick Matos | 2 | 54 | 3.98 |
| Alan Mishchenko | 3 | 982 | 84.79 |
| André Inácio Reis | 4 | 134 | 21.33 |
| Renato P. Ribas | 5 | 204 | 33.52 |