Name
Abstract | ||
|---|---|---|
The manufacturing yield challenge of 3-D integrated circuit is one of the key obstacles in the industry adoption of 3-D integration based on through-silicon-vias (TSVs). The addition of spare TSVs to repair faulty functional TSVs (f-TSVs) is an effective method for yield and reliability enhancement, but this approach results in significant hardware cost and delay overhead. Most existing solutions are only suitable for a “dual-uniform” scenario in which both the placement and the defect probabilities of f-TSVs are assumed to be uniform. In this paper, we propose a design technique that is compatible with nonuniform TSV placement and it can repair faulty TSVs based on a realistic clustered defect-distribution model. The proposed solution is based on two consecutive stages, which utilize a greedy algorithm and an integer-linear-programming formulation, respectively. By considering the tradeoff between chip yield, hardware cost, and delay overhead, the proposed technique provides higher yield and reliability under a clustered defect distribution, and with minimum hardware cost and delay overhead, compared to the previous work. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/tcad.2018.2864291 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
Through-silicon vias,Resource management,Delays,Stress,Three-dimensional displays,Circuit faults | Resource management,Spare part,Computer science,Effective method,Electronic engineering,Greedy algorithm,Chip,Cluster analysis,Integrated circuit,Reliability engineering | Journal |
Volume | Issue | ISSN |
38 | 10 | 0278-0070 |
Citations | PageRank | References |
1 | 0.37 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shengcheng Wang | 1 | 13 | 4.29 |
| K Chakrabarty | 2 | 8173 | 636.14 |
| Mehdi B. Tahoori | 3 | 1537 | 163.44 |