Name
Abstract | ||
|---|---|---|
Standard cell libraries have been successfully used for years, however with the emergence of new technologies and the increasing complexity of designs, this concept becomes less and less attractive. Most of the time, cells are too generic and not well suited to the block being created. As a result the final design is not well optimized in terms of timing, power and area.This paper describes a new approach based on transistor level layout synthesis for CMOS IP cores rapid prototyping (~100k transistors). |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1007/3-540-45716-X_16 | PATMOS |
Keywords | Field | DocType |
transistor level layout synthesis,increasing complexity,cmos ip core,new technology,standard cell library,transistor level,final design,new approach,p. prototyping,rapid prototyping | Rapid prototyping,Logic synthesis,Computer science,Circuit design,Electronic engineering,CMOS,Electronic design automation,Standard cell,Transistor,Integrated circuit,Embedded system | Conference |
ISBN | Citations | PageRank |
3-540-44143-3 | 0 | 0.34 |
References | Authors | |
7 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. Landrault | 1 | 0 | 1.35 |
| L. Pellier | 2 | 0 | 0.34 |
| A. Richard | 3 | 0 | 0.34 |
| C. Jay | 4 | 0 | 0.34 |
| Michael Robert | 5 | 0 | 0.34 |
| Daniel Auvergne | 6 | 145 | 31.67 |