Name
Abstract | ||
|---|---|---|
In this paper, we propose a novel on-chip circuit to measurethe jitter present at the output of Phase-Locked-Loops(PLLs) used for synthesizing a clock with equal or higherfrequency than the input clock.This measure is performedat every period of the ... |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/IOLTS.2004.12 | IOLTS |
Keywords | Field | DocType |
test-per-scan bist,novel on-chip circuit,input clock,jitter present,automatic test pattern generation,hardware,linear feedback shift register,shift registers,degradation,compaction,feedback,informatics,arithmetic,lfsr,arithmetic function | Automatic test pattern generation,Heuristic,Arithmetic function,Shift register,Computer science,Arbitrary-precision arithmetic,Algorithm,Electronic engineering,Test compression,Accumulator (structured product),Built-in self-test | Conference |
ISBN | Citations | PageRank |
0-7695-2180-0 | 1 | 0.40 |
References | Authors | |
6 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| P. Karpodinis | 1 | 1 | 0.40 |
| D. Kagaris | 2 | 117 | 11.32 |
| D. Nikolos | 3 | 291 | 31.38 |