Name
Abstract | ||
|---|---|---|
We present a layout synthesis methodology based on the use of virtual CMOSlibraries, i.e. using no pre-characterized cells. The proposed methodology isorganized around an automatic layout generator, allowing fast on-the-flyimplementation of macro-cells. The generator eliminates the need for postlayoutcompaction procedures and in addition produces parasitic capacitancesestimations. Results show that it is possible to quickly generate dense layouts,allowing fast prototyping of logic... |
Year | Venue | Keywords |
|---|---|---|
1999 | VLSI | east layout synthesis,virtual cmos library approach |
Field | DocType | ISBN |
Computer science,CMOS,Electronic engineering,Physical design | Conference | 0-7923-7731-1 |
Citations | PageRank | References |
3 | 0.66 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| F. Moraes | 1 | 3 | 0.66 |
| Michel Robert | 2 | 3 | 0.66 |
| Daniel Auvergne | 3 | 145 | 31.67 |