Paper Info
Title
Random access schemes for efficient FPGA SpMV acceleration.
Abstract
Utilizing hardware resources efficiently is vital to building the future generation of high-performance computing systems. The sparse matrix - dense vector multiplication (SpMV) kernel, which is notorious for its poor efficiency on conventional processors, is a key component in many scientific computing applications and increasing SpMV efficiency can contribute significantly to improving overall system efficiency. The major challenge in implementing SpMV efficiently is handling the input-dependent memory access patterns, and reconfigurable logic is a strong candidate for tackling this problem via memory system customization. In this work, we consider three schemes (all off-chip, all on-chip, caching) for servicing the irregular-access component of SpMV and investigate their effects on accelerator efficiency. To combine the strengths of on-chip and off-chip random accesses, we propose a hardware-software caching scheme named NCVCS that combines software preprocessing with a nonblocking cache to enable highly efficient SpMV accelerators with modest on-chip memory requirements. Our results from the comparison of the three schemes implemented as part of an FPGA SpMV accelerator show that our scheme effectively combines the high efficiency from on-chip accesses with the capability of working with large matrices from off-chip accesses.
Year
DOI
Venue
2016
10.1016/j.micpro.2016.02.015
Microprocessors and Microsystems - Embedded Hardware Design
Keywords
Field
DocType
Sparse matrix–vector multiplication,FPGA,Memory system,Cache,Efficiency
Kernel (linear algebra),Cache,Computer science,Sparse matrix-vector multiplication,Parallel computing,Field-programmable gate array,Real-time computing,Software,Multiplication,Sparse matrix,Random access
Journal
Volume
Issue
ISSN
47
PB
0141-9331
Citations 
PageRank 
References 
1
0.34
0
Authors
2
Name
Order
Citations
PageRank
Yaman Umuroglu118610.67
Magnus Jahre222620.50