Name
Abstract | ||
|---|---|---|
This paper presents a novel approach for testing multi-port memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory. The parallelization is based on partitioning the memory into so-called segments; in each phase, the operation of a port is restricted to a segment. The proposed approach utilizes parallel segment accesses by arranging the ports on a pair-wise basis (one port for reading and the second port for writing); this permits an efficient utilization of the ports and full coverage of inter-port faults for both normal and mirror layouts. A port assignment process is utilized together with the partitioning of the memory; it considers the functionalities of the ports and their relation with respect to the addresses and the placement of the cells. It is shown that the test complexity of the proposed approach is independent of the number of ports. Simulation results are presented. A BIST circuitry capable of embedding and controlling this parallel approach is also proposed; it is shown that the BIST implementation is O(NlogN) where N is the number of ports. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1016/S0026-2692(02)00124-6 | Microelectronics Journal |
Keywords | Field | DocType |
Memory testing,Embedded memory,Multi-port,Parallel testing | Design for testing,Port (computer networking),Coupling,Embedding,Computer science,Parallel computing,Subdivision,Time complexity,Built-in self-test,Random access | Journal |
Volume | Issue | ISSN |
34 | 1 | 0026-2692 |
Citations | PageRank | References |
2 | 0.48 | 5 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| F. Karimi | 1 | 8 | 1.69 |
| S. Irrinki | 2 | 24 | 2.21 |
| T. Crosby | 3 | 4 | 0.89 |
| N. Park | 4 | 39 | 7.43 |
| F. Lombardi | 5 | 232 | 24.13 |