Name
Abstract | ||
|---|---|---|
Cofactorization, checking smoothness of mid-size integers, is usually adopted in General Number Field Sieve. In this paper, we present a specific cofactorization hardware implementation, which performs smoothness test for mid-size integers at a much higher throughput than previous works. The proposed design, based on highly-parallel and pipeline structure, can analysis a 125-bit integer and determine in less than 130 clock cycles whether it could factor completely over a factor base. Besides, the algorithm used in architecture can be performed by multiplication, addition and some logical operations only, which brings simple circuit structure, low hardware cost and short time delay. Moreover, the comparison results show that our architecture achieves a speedup of one or two orders of magnitude over implementation based on Elliptic Curve Method. Our design therefore can be a good solution to cofactorization. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/CITS.2016.7546388 | 2016 International Conference on Computer, Information and Telecommunication Systems (CITS) |
Keywords | Field | DocType |
Cofactorization,smoothness test,prime factor,divisibility,pipeline structure | Integer,Factor base,Multiplication,Hamming weight,Throughput,Computer hardware,Smoothness,General number field sieve,Mathematics,Speedup | Conference |
ISSN | ISBN | Citations |
2326-2338 | 978-1-5090-0691-5 | 0 |
PageRank | References | Authors |
0.34 | 3 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Haibo Yu | 1 | 50 | 7.36 |
| Guoqiang Bai | 2 | 75 | 14.56 |