Guoqiang Bai - Citegraph

Author Info

Name	Affiliation	Papers
GUOQIANG BAI	Institute of Micro Electronics, Tsinghua University, Beijing, People's Republic of China 100084	35
Collaborators	Citations	PageRank
36	75	14.56
Referers	Referees	References
159	370	233

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100370

Publications (35 rows)

Collaborators (36 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Hardware Implementation Of Convolutional Neural Network For Face Feature Extraction	0	0.34	2019
Efficient Hardware Implementation of Roadrunner for Lightweight Application	0	0.34	2016
A Very Compact Masked S-Box for High-Performance Implementation of SM4 Based on Composite Field.	0	0.34	2016
High-Speed Polynomial Multiplier Architecture for Ring-LWE Based Public Key Cryptosystems.	4	0.45	2016
Detecting first-order leakages against the tower field masking scheme	0	0.34	2016
A Family of Scalable Polynomial Multiplier Architectures for Ring-LWE Based Cryptosystems.	0	0.34	2016
Specific hardware implementation for cofactorization in GNFS	0	0.34	2016
Towards efficient discrete Gaussian sampling for lattice-based cryptography	3	0.41	2015
Improving Second-Order DPA Attacks with New Modeled Power Leakages.	0	0.34	2015
An efficient method for integer factorization	2	0.46	2015
Strategy of Relations Collection in Factoring RSA Modulus.	0	0.34	2015
A Family of Scalable Polynomial Multiplier Architectures for Lattice-Based Cryptography	0	0.34	2015
Ultra High-Performance ASIC Implementation of SM2 with SPA Resistance.	0	0.34	2015
A Family of Scalable Polynomial Multiplier Architectures for Lattice-Based Cryptography	0	0.34	2015
Towards Efficient Implementation of Lattice-Based Public-Key Encryption on Modern CPUs	0	0.34	2015
Efficient Modular Reduction Algorithm Without Correction Phase.	0	0.34	2015
On trojan side channel design and identification	2	0.36	2014
Ultra High-Speed SM2 ASIC Implementation	2	0.35	2014
Attacks on Physically-Embedded Data Encryption for Embedded Devices	0	0.34	2014
Exploring the speed limit of SM2	0	0.34	2014
A Novel Relative Frequency Based Ring Oscillator Physical Unclonable Function	2	0.40	2014
A randomized window-scanning RSA scheme resistant to power analysis	1	0.36	2014
A Novel Technique for Ring Oscillator Based PUFs to Enroll Stable Challenge Response Pairs	0	0.34	2014
Integration of information security chips based on System-in-Package	0	0.34	2011
Design and implementation of pipelined TMVP multiplier using block recombination	0	0.34	2011
A Gbps IPSec SSL Security Processor Design and Implementation in an FPGA Prototyping Platform	4	0.52	2010
A DPA-Resistant Digit-Parallel Modular Multiplier over GF (2m)	1	0.34	2009
A New Method to Reduce the Side-Channel Leakage Caused by Unbalanced Capacitances of Differential Interconnections in Dual-Rail Logic Styles	0	0.34	2009
A dual-field elliptic curve cryptographic processor based on a systolic arithmetic unit	3	0.45	2008
Zodiac: System architecture implementation for a high-performance Network Security Processor	6	0.58	2008
A New Systolic Architecture for Modular Division	4	0.49	2007
A High-Performance Elliptic Curve Cryptographic Processor for General Curves Over GF(p) Based on a Systolic Arithmetic Unit	36	1.57	2007
A Novel Unified Control Architecture for a High-Performance Network Security Accelerator	2	0.50	2007
Stability conditions for discrete hopfield neural networks with delay	3	0.56	2006
Convergence study of discrete neural networks with delay	0	0.34	2006