Name
Title | ||
|---|---|---|
Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits. |
Abstract | ||
|---|---|---|
In three-dimensional integrated circuits (3DICs) aggressive wafer-thinning can lead to large thermal gradients, including spikes in individual device temperatures. In a non-thinned circuit, the large bulk silicon wafer on which devices are built works as a very good thermal conductor, enabling heat to diffuse laterally. In this paper we experimentally examine the thermal resistance from an active on-chip heater to the heatsink in a two-tier bump-bonded 3D stacked system. A simplified structure is introduced to enable such measurements without the time and cost associated with the full fabrication of such a system. Die thinning is seen to have a pronounced effect on the thermal response, which can adversely affect system reliability. Thinning the top tier from 725μm to 20μm resulted in a nearly 4 times increase in the normalized temperature rise of the heater of our test chip. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1016/j.microrel.2016.08.015 | Microelectronics Reliability |
Keywords | Field | DocType |
3DIC,Die thinning,Thermal resistance,Integrated circuit | Wafer,Thermal,Computer science,Electronic engineering,Die (manufacturing),Heat sink,Electrical engineering,Optoelectronics,Integrated circuit,Fabrication,Thermal resistance,Thermal conductivity | Journal |
Volume | ISSN | Citations |
67 | 0026-2714 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Samson Melamed | 1 | 54 | 6.41 |
| Watanabe, N. | 2 | 3 | 3.63 |
| Shunsuke Nemoto | 3 | 0 | 1.01 |
| Haruo Shimamoto | 4 | 0 | 0.34 |
| Katsuya Kikuchi | 5 | 3 | 3.63 |
| Masahiro Aoyagi | 6 | 8 | 9.86 |