Name
Abstract | ||
|---|---|---|
With technology down scaling, static power has become one of the biggest challenges in a system on chip. Normally off computing using nonvolatile (NV) sequential elements is a promising solution to address this challenge. Recently, many NV shadow flip-flop architectures have been introduced in which magnetic tunnel junction (MTJ) cells are employed as backup storing elements. Due to the emerging fabrication processes of magnetic layers, MTJs are more susceptible to manufacturing defects than their CMOS counterparts. Moreover, unlike memory arrays that can effectively be repaired with well-established memory repair and coding schemes, flip-flops scattered in the layout are more difficult to repair. Therefore, without effective defect and fault tolerance for NV flip-flops, the manufacturing yield will be affected severely. In this paper, we propose a fault-tolerant NV latch (FTNV-L) design, in which several MTJ cells are arranged in such a way that it is resilient to various MTJ faults. The simulation results show that our proposed FTNV-L can effectively tolerate all single MTJ faults with a considerably lower overhead than traditional approaches. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TVLSI.2016.2630315 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
Magnetic tunneling,Tunneling magnetoresistance,Resistance,Latches,Magnetization,Manufacturing,Circuit faults | System on a chip,Computer science,FLOPS,Electronic engineering,CMOS,Fault tolerance,Process variation,Tunnel magnetoresistance,Flip-flop,Backup,Embedded system | Journal |
Volume | Issue | ISSN |
25 | 4 | 1063-8210 |
Citations | PageRank | References |
3 | 0.41 | 14 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rajendra Bishnoi | 1 | 132 | 19.64 |
| Fabian Oboril | 2 | 288 | 26.71 |
| Mehdi B. Tahoori | 3 | 1537 | 163.44 |