Name
Abstract | ||
|---|---|---|
3D heterogeneous processor (commonly termed as 3DHP) integrating multiple processor (such as CPU/GPU) and DRAM dies vertically interconnected by a massive number of Through-Silicon Vias (TSVs) is expected to address the limited bandwidth, high latency and energy consumption of off-chip DRAM. However, spatial and temporal variability due to hotspots in on-chip thermal gradient may result in wide bit error rate variation in DRAM dies. A multi-path BCH decoder has been recently proposed to efficiently address this issue. In this paper, a novel parallel decoding approach for the Multi-Stage BCH decoder is proposed and validated. The proposed approach efficiently leverages the multiple decoding paths to decode multiple words and minimizes the overall decoding latency. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ISOCC.2016.7799756 | 2016 International SoC Design Conference (ISOCC) |
Keywords | Field | DocType |
bit error rate variation,3DHP,on-chip thermal gradient,spatial variability,temporal variability,energy consumption,off-chip DRAM,TSVs,through-silicon vias,DRAM dies,3D heterogeneous processor,multistage BCH decoder,parallel decoding approach | Dram,Latency (engineering),Computer science,Parallel computing,Real-time computing,BCH code,Bandwidth (signal processing),Soft-decision decoder,Decoding methods,Computer hardware,Energy consumption,Bit error rate | Conference |
ISSN | ISBN | Citations |
2163-9612 | 978-1-5090-3220-4 | 0 |
PageRank | References | Authors |
0.34 | 2 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Prashanthi Metku | 1 | 0 | 2.70 |
| Ramu Seva | 2 | 0 | 1.69 |
| Kyung Ki Kim | 3 | 99 | 21.62 |
| Yong-Bin Kim | 4 | 22 | 7.14 |
| Minsu Choi | 5 | 156 | 27.63 |