Paper Info
Title
MorphoNoC: Exploring the Design Space of a Configurable Hybrid NoC using Nanophotonics.
Abstract
As diminishing feature sizes drive down the energy for computations, the power budget for on-chip communication is steadily rising. Furthermore, the increasing number of cores is placing a huge performance burden on the network-on-chip (NoC) infrastructure. While NoCs are designed as regular architectures that allow scaling to hundreds of cores, the lack of a flexible topology gives rise to higher latencies, lower throughput, and increased energy costs. In this paper, we explore MorphoNoCs - scalable, configurable, hybrid NoCs obtained by extending regular electrical networks with configurable nanophotonic links. In order to design MorphoNoCs, we first carry out a detailed study of the design space for Multi-Write Multi-Read (MWMR) nanophotonics links. After identifying optimum design points, we then discuss the router architecture for deploying them in hybrid electronic-photonic NoCs. We then study the design space at the network level, by varying the waveguide lengths and the number of hybrid routers. This affords us to carry out energy-latency trade-offs. For our evaluations, we adopt traces from synthetic benchmarks as well as the NAS Parallel Benchmark suite. Our results indicate that MorphoNoCs can achieve latency improvements of up to 3.0× or energy improvements of up to 1.37× over the base electronic network.
Year
DOI
Venue
2017
10.1016/j.micpro.2017.03.006
Microprocessors and Microsystems
Keywords
DocType
Volume
Network-on-Chip,Nanophotonics,Reconfigurable networks,Design-space exploration,Optical interconnects
Journal
50
ISSN
Citations 
PageRank 
0141-9331
0
0.34
References 
Authors
16
5
Name
Order
Citations
PageRank
Vikram K. Narayana110213.18
Shuai Sun211.76
A. A. Badawy36716.88
J Sorger4789.98
tarek elghazawi569784.30