Title
Multiple-loop design technique for high-performance low dropout regulator
Abstract
In portable mobile devices, the power management IC unit (PMIC) requires many low-dropout voltage regulators (LDO) with different output voltages and load current capacities to support many applications; such as Application Processor (AP), Camera, Memory, RFIC Transceivers, USB, etc. For example, the PMIC in mobile phone Galaxy S6/S7 needs more than 50 LDOs to support the above applications, which require an extremely big quiescent current that degrade battery life time. Reducing quiescent current of LDO while maintaining system's operation is critical; however, there is a big trade-off between quiescent current and other LDO's characteristics such as undershoot/overshoot, PSRR, noise, etc. This paper proposed a new multiple-loop design technique for LDO that offer very low quiescent current (more than 50% reduction); however, excellent performance improvement compared to prior reported works. The design has been successfully implemented in many products of Samsung for mobile phone, Table PCs, etc.
Year
DOI
Venue
2016
10.1109/ASSCC.2016.7844174
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Keywords
Field
DocType
LDO,fast-transient,dynamic-biasing
Power management,Computer science,Voltage,Electronic engineering,Power supply rejection ratio,RFIC,Electrical engineering,Voltage regulator,Low-dropout regulator,USB,Performance improvement
Conference
ISBN
Citations 
PageRank 
978-1-5090-3701-8
0
0.34
References 
Authors
1
8
Name
Order
Citations
PageRank
Quoc-Hoang Duong140.75
Jeong-Woon Kong240.75
Hyeon-Seok Shin300.34
Huy-Hieu Nguyen4547.46
Pan-Jong Kim500.34
Yu-Seok Ko640.75
Hwa-Yeoul Yu700.34
Ho-Jin Park8366.77