Name
Abstract | ||
|---|---|---|
Approximate computing is an attractive design methodology to achieve low power, high performance (low delay) and reduced circuit complexity by relaxing the requirement of accuracy. In this paper, approximate Booth multipliers are designed based on approximate radix-4 modified Booth encoding (MBE) algorithms and a regular partial product array that employs an approximate Wallace tree. Two approxima... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TC.2017.2672976 | IEEE Transactions on Computers |
Keywords | Field | DocType |
Logic gates,Delays,Image coding,Encoding,Power demand,Adders | Logic gate,Circuit complexity,Adder,Computer science,Parallel computing,Algorithm,Multiplier (economics),CMOS,Encoder,Wallace tree,Encoding (memory) | Journal |
Volume | Issue | ISSN |
66 | 8 | 0018-9340 |
Citations | PageRank | References |
17 | 0.73 | 19 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| weiqiang liu | 1 | 135 | 28.76 |
| Liangyu Qian | 2 | 17 | 0.73 |
| chenghua wang | 3 | 83 | 12.73 |
| Honglan Jiang | 4 | 150 | 9.50 |
| Jie Han | 5 | 863 | 66.92 |
| F. Lombardi | 6 | 122 | 15.25 |